Charge pump element with body effect cancellation for early charge pump stages

ABSTRACT

A charge pump stage comprising a pulse train which injects energy into a gate of a charge transfer transistor of the charge pump stage, wherein a modified output of the pulse train is input to a bulk of the charge transfer transistor such that a bulk voltage of the charge transfer transistor is raised to a level not greater than the minimum of a source voltage and a drain voltage of that charge transfer transistor. A method for operating the charge pump stage is also disclosed.

FIELD OF THE INVENTION

[0001] The present invention relates generally to charge pumps forboosting voltages in microelectronic circuitry, and particularly to acharge pump stage architecture with body effect minimization.

BACKGROUND OF THE INVENTION

[0002] Non-volatile memory arrays, such as erasable, programmable readonly memory (EPROM) or flash memory arrays, or electrically erasable,programmable read only memory (EEPROM) arrays, require high positive ornegative voltages to program and erase memory cells of the array.Typically, these voltages are higher than the voltage supplied (Vdd).Charge pumps are generally used to boost on-chip voltages above thesupply voltage Vdd to reach the voltages required for programming orerasing.

[0003] A charge pump typically comprises cascaded stages thatprogressively boost the voltage to higher levels. The charge pumpfunctions by progressively storing more charge on a capacitor which ispart of a capacitor-diode combination, with several such stages beingplaced together in a network to obtain the desired increase in voltage.The diode functions to prevent discharge of the capacitor prior toplacing the additional charge thereon.

[0004] Reference is now made to FIGS. 1 and 2, which respectivelyillustrate four stages and a single stage of a commonly used charge pumparchitecture, called a four-phased-clock, threshold-voltage-cancelingpump architecture, for a four-stage charge pump (see Umezawa, IEEEJournal of Solid State Circuits, Vol. 27, 1992, page 1540).

[0005] The charge pump circuit includes a plurality of charge transfertransistors (reference letters m_(i)) connected in series. In FIG. 1,four such charge transfer transistors are shown, labeled m₁, m₂, m₃ andm₄. In FIG. 2, which shows a single stage, one charge transfertransistor m_(i) is shown. Charge transfer transistors m_(i) may use,but are not limited to, CMOS (complementary metal oxide semiconductor)technology, being either n-channel or p-channel (NMOS or PMOS) fieldeffect transistors (FETs). FIGS. 1 and 2 illustrate a positive chargepump based on NMOS. It is noted that NMOS is generally used to pumppositive voltages, whereas PMOS is generally used to pump negativevoltages. The charge transfer transistors have a control electrode(gate, labeled g), a first electrode (drain, labeled d) and a secondelectrode (source, labeled s), connected to nodes, as describedhereinbelow. (Since MOSFETs are typically symmetrical components, thetrue designation of “source” and “drain” is only possible once a voltageis impressed on the terminals of the transistors. The designations ofsource and drain throughout the specification should be interpreted,therefore, in the broadest sense.) Preferably, the bulks (labeled b) ofthe charge transfer transistors m_(i) are coupled to a reference lineREF (FIG. 2) for receiving a reference voltage, generally ground in thecase of NMOS.

[0006] Referring to FIG. 1, the source of charge transfer transistor m₁is connected to node n₀, which is connected to Vdd. The gate of chargetransfer transistor m₁ is connected to node g₁, and the drain isconnected to node n₁. (In the general single stage shown in FIG. 2, thesource of charge transfer transistor mi is connected to node n_(i−1) thegate is connected to node g_(i), and the drain is connected to noden_(i).) The source of charge transfer transistor m₂ is connected to noden₁, the gate is connected to node g₂, and the drain is connected to noden₂. Similarly, the source of charge transfer transistor m₃ is connectedto node n₂, the gate to node g₃, and the drain to node n₃. Likewise, thesource of charge transfer transistor m₄ is connected to node n₃, thegate to node g₄, and the drain to node n₄.

[0007] Two-phase pulse trains PH1 and PH2, and PH1A and PH2A areprovided (FIG. 1), such as from a pulse generator (not shown). The PH1and PH1A phases may be non-overlapping with respect to each other, andthe PH2 and PH2A phases may be non-overlapping with respect to eachother. The PH1 and PH2 phase may be overlapping. By non-overlapping itis meant that 0 to 1, and 1 to 0 voltage transitions of one pulse neveroverlap with the transitions of the other pulse. The PH1 and PH2 phasesinject energy into the pump through large capacitors 5 into nodes n_(i).Accordingly, in the illustrated embodiment, a large capacitor 5 isconnected from pulse train PH1 to node n₁, and another large capacitor 5is connected from pulse train PH1 to node n₃. Another large capacitor 5is connected from pulse train PH2 to node n₂, and another largecapacitor 5 is connected from pulse train PH2 to node n₄. The charge istransferred along the pump through charge transfer transistors m_(i)connecting node n_(i) to node n_(i+1). (In the general single stageshown in FIG. 2, large capacitor 5 is connected from pulse train PH tonode n_(i).)

[0008] The PH1A and PH2A phases inject energy into the pump throughsmall capacitors 11 into nodes g_(i). Capacitors 11 preferably have amuch smaller capacitance than large capacitors 5. In the illustratedembodiment a small capacitor 11 is connected from pulse train PH1A tonode g₂, and another small capacitor 11 is connected from pulse trainPH1A to node g₄. Another small capacitor 11 is connected from pulsetrain PH2A to node g₁, and another small capacitor 11 is connected frompulse train PH2A to node g₃. (In the general single stage shown in FIG.2, small capacitor 11 is connected from pulse train PHA to node g_(i).)

[0009] As seen in FIGS. 1, a plurality of auxiliary transistors t_(i)(i.e., t₁, t₂, t₃ and t₄) are provided. In FIG. 2, which shows a singlestage, one auxiliary Transistor t_(i) is shown. Each auxiliarytransistor t_(i) has its drain connected to the gate node g_(i) of eachcharge transfer transistor m_(i) (i.e., m₁, m₂, m₃ and m₄, respectively,in FIG. 1). The source of each auxiliary transistor t_(i) is connectedto the source of each charge transfer transistor m_(i) (i.e., noden_(i−1)). The gate of each auxiliary transistor t_(i) is connected tothe drain of each charge transfer transistor m_(i) (i.e., node n_(i)).The bulk of each auxiliary transistor t_(i) is connected to the bulk ofeach charge transfer transistor m_(i), which is generally grounded. Theauxiliary transistors t_(i) and the PH1A and PH2A phases (PHA in thesingle stage shown in FIG. 2) and small capacitors 11 may control thegate voltage of the charge transfer transistors m_(i).

[0010] The operation of the first stage of the pump is now explained,with all subsequent stages operating in the same manner. The operationcommences with the PH1 phase starting to rise. Initially, chargetransfer transistors m₁ and m₂ are non-conducting (i.e., turned off),since the PH1A and PH2A phases arc in their low phase. The PH1 phasethen fully rises and injects energy into node n₁, raising (or “pushing”)node n₁ to a voltage boosted above Vdd, such as 2 Vdd. The rise of noden₁ forces node g₁ to Vdd through auxiliary transistor t₁. Since thesource of charge transfer transistor m₁ is connected to Vdd at node no,the gate-source voltage bias V_(gs) of charge transfer transistor m₁ iszero, assuring that transistor m₁ is turned off.

[0011] After a short time, typically in the order of severalnanoseconds, the PH1A phase rises, which makes charge transfertransistor m₂ conduct (i.e., turns on). During this time, node n₁ is ata higher voltage than node n₂. Since, as just mentioned, charge transfertransistor m₂ is conducting, charge is transferred from node n₁ to noden₂. During the next phase, the PH2 phase rises and the PH1 phase drops.This causes node n₁ to drop and node n₂ to rise, thereby causing chargeto be transferred from node n₂ to node n₃. In this manner charge istransferred along the pump. Each of the g_(i) nodes is raised by a Vddlevel with respect to the n_(i) nodes when charge transfer is takingplace. In the latter stages of the pump, the source and drain nodes(i.e., nodes n₃ and n₄) are raised well above the bulk, which is usuallygrounded.

[0012] In the more general case of a single stage, shown in FIG. 2, thecharge is injected into the stage when the PH signal of the previousstage is high, and is transferred across the charge transfer transistorm_(i) when the PHA signal is high. Note that when comparing node n⁻¹ ton_(i), the average voltage of n_(i) is greater than that of n_(i−1).However, during the stage when charge is transferred from n¹⁻¹ to n_(i),the voltage of n_(i−1) is briefly higher than that of n_(i).

[0013] The large voltage difference between the high source/drainvoltages and the low bulk voltage causes a problem, called the body orbulk effect, which is now explained. (The terms body and bulk are usedinterchangeably throughout the specification and claims.)

[0014] Positive charge pumps generally use NMOS transistors, and thisrequires the body of the charge transfer transistors to be at the lowestvoltage, in general ground (GND). (Negative charge pumps have theopposite requirement, and PMOS transistors are generally used.) However,in positive charge pumps there can be a significant loss of energy inthe latter pump stages due to the “body effect”. In NMOS, the bodyeffect causes an increase in the threshold voltage (V_(t)), due to thefact that the bulk or body of the transistor is at a lower voltage thanthe source. Due to the body effect, the threshold voltage V_(t) of theNMOS transistors progressively increases from the stages near the inputterminal of the charge pump to the stages near the output terminal. Forexample, in the prior art charge pump of FIG. 1, the threshold voltageV_(t) of charge transfer transistors m_(i) progressively increases fromtransistor m_(i) to transistor m₄. In transistor m₄, as mentionedhereinabove, the source and drain nodes n₃ and n₄, have been raised wellabove the bulk. This reduces the efficiency of the charge pump, becausethe charge transfer through each stage decreases.

[0015] In some CMOS processes, such as triple-well andsilicon-on-insulator (SOI), it is possible to raise the bulk of the NMOScharge transfer transistors above the grounded substrate, which wouldreduce the body effect by diminishing the voltage difference between thebulk and the source/drain. However, in the prior art, this entailscertain risks. For example, if the bulk voltage is raised above thesource or drain voltage, then parasitic bipolar transistors (typicallyfound in CMOS processes) can turn on, which can cause either latchup ordrain the charge from the pump.

[0016] In many circuits, not necessarily charge pumps, the bulk effectis eliminated by connecting the bulk node to the source node. This isnot possible in a charge pump, however, because the “source” can behigher or lower than the “drain” by Vdd, depending upon the clock cycle.This would cause parasitic diodes to turn on, resulting in the unwantedbipolar transistor turn-on and latchup.

[0017] One method for compensating for the body effect is described inU.S. Pat. No. 6,064,251 to Park. Park uses charge pump stages coupled inseries. Each charge pump is stage has two clock terminals that receivetwo phase shifted clock signals. The charge pump stages are configuredso that adjacent charge pump stages receive different clock signals. Thephases of the clock signals arc such that the pump elements are boostedwell above the threshold voltage V_(t), thereby providing thetransistors with sufficient overdrive to transfer energy along the pump.However, clock boosting uses a significant amount of power consumptionand is thus very inefficient.

[0018] Another prior attempt to minimize the bulk effect is described inU.S. patent application Ser. No. 09/826,351, assigned to the sameassignee of the present invention, the disclosure of which isincorporated herein by reference. This method is effective in the latterpump stages (from the fourth stage onwards). In this case, the bulk ofthe stage is boosted by a source follower circuit whose gate isconnected to the output of a previous stage at a voltage V, boosting thebulk to V-V_(t), where V_(t) is the threshold voltage of the sourcefollower.

[0019]FIG. 3 illustrates a single stage of the source follower circuitof U.S. patent application Ser. No. 09/826,351. NMOS charge transfertransistor m; has its source connected to node n_(i−1), its gateconnected to node g_(i), and its drain connected to node n_(i). Pulsetrain PH injects energy into the pump through large capacitor 5connected to node n_(i). Another pulse train PHA injects energy into thepump through small capacitor 11 into node g_(i).

[0020] An auxiliary transistor t_(i) has its drain connected to the gatenode g_(i) of charge transfer transistor m_(i). The source of auxiliarytransistor t_(i) is connected to the source of charge transfertransistor m_(i) (i.e., node n_(i−1)). The gate of auxiliary transistort_(i) is connected to the drain of charge transfer transistor m_(i)(i.e., node n_(i)). The auxiliary transistor t_(i) and the PHA phasecontrol the gate voltage of the charge transfer transistor m_(i). TheP-well (PW) of the transistors is isolated from the P-substrate, such asby a triple well process.

[0021] An additional transistor s_(i) is preferably configured as asource follower. A source follower is a method of configuring a FET,wherein the output voltage is at the source, and it “follows” the inputvoltage, which is connected to the gate. By “following” it is meant thatthe output voltage equals the input voltage minus the threshold voltage.The input of the source follower s_(i) is from a previous pump stage andis used to drive the bulk of a subsequent pump stage.

[0022] In the circuitry of FIG. 3, the gate of source follower s_(i) isconnected to the drain of charge transfer transistor m_(i−2). The sourceand bulk of source follower s_(i) are connected to the bulk of chargetransfer transistor m_(i) and to the bulk of auxiliary transistor t_(i)via a node p_(i) and a node q_(i). Node p_(i) may be connected to ableeder element 12, which may be, without limitation, a current source.The drain of source follower s_(i) is connected to a high voltage, suchas at a node w_(i), which may be the pump output or the stage output orinput, for example

[0023] The disadvantage of this method is that it only provides asolution for the latter pump stages. In the earlier stages, there isalso a significant bulk effect, which can deteriorate the pump'sefficiency. There is accordingly a need for a method to efficientlycompensate for the bulk effect in the early pump stages, without openingthe parasitic bipolar transistors.

SUMMARY OF THE INVENTION

[0024] The present invention provides a novel charge pump stage forpumping high positive voltages, which minimizes the abovementioned bodyeffect. In the present invention, the method may boost the bulk voltageat any stage, even at the early pump stages.

[0025] There is thus provided hi accordance with an embodiment of thepresent invention a method for operating a charge pump, the methodcomprising providing a pulse train which injects energy into a chargepump stage to a gate of a charge transfer transistor of the charge pumpstage, and inputting a modified output from the pulse train to a bulk ofthe charge transfer transistor such that a bulk voltage of the chargetransfer transistor is raised to a level not greater than the minimum ofa source voltage and a drain voltage of that charge transfer transistor.

[0026] In accordance with an embodiment of the present invention thebulk voltage of the charge pump stage is raised to a level below aminimum of source/drain voltages of a charge transfer transistor at thatstage.

[0027] Further in accordance with an embodiment of the present inventionmodifying the output comprises connecting the pulse train to an input ofa first inverter, which outputs to a second inverter, wherein an outputof the second inverter is connected to the bulk of the charge transfertransistor.

[0028] Still further in accordance with an embodiment of the presentinvention the method comprises providing an n-channel metal oxidesemiconductor (NMOS) transistor, wherein a source of the NMOS transistoris connected to a positive supply of the second inverter, a gate of theNMOS transistor is connected to the drain of the charge transfertransistor, and a drain of the NMOS transistor is connected to a supplyvoltage (Vdd) of the charge pump stage.

[0029] In accordance with an embodiment of the present invention thesource voltage of the NMOS transistor (Vs) is the minimum of Vdd and thedifference between the voltage of the stage output and the thresholdvoltage of the NMOS transistor.

[0030] Further in accordance with an embodiment of the present inventionthe bulk of the NMOS transistor is connected to its source.

[0031] There is also provided in accordance with an embodiment of thepresent invention a charge pump stage comprising a pulse train whichinjects energy into a gate of a charge transfer transistor of the chargepump stage, wherein a modified output or the pulse train is input to abulk of the charge transfer transistor such that a bulk voltage off thecharge transfer transistor is raised to a level not greater than theminimum of a source voltage and a drain voltage of that charge transfertransistor.

BRIEF DESCRIPTION OF THE DRAWINGS

[0032] The present invention will be understood and appreciated morefully from the following detailed description taken in conjunction withthe drawings in which:

[0033]FIGS. 1 and 2 are simplified circuit diagrams of a charge pumparchitecture commonly used in the prior art, comprising athreshold-voltage-canceling four-phased charge pump, wherein FIG. 1illustrates four stages of the charge pump and FIG. 2 illustrated asingle stage of the charge pump;

[0034]FIG. 3 is a simplified circuit diagram of a charge pump stage witha boosted well of the prior art, wherein the bulk of the stage isboosted by a source follower circuit;

[0035] In FIG. 4 is a simplified circuit diagram of a charge pump stagewith a boosted well, constructed and operative in accordance with anembodiment of the present invention; and

[0036]FIG. 5 is a simplified graphical illustration of simulatedwaveforms for the charge pump stage of FIG. 4, in accordance with apreferred embodiment of the present invention.

DETAILED DESCRIPTION OF A PREFERRED EMBODIMENT

[0037] Reference is now made to FIG. 4, which illustrates a charge pumpstage 20 with a boosted well, constructed and operative in accordancewith an embodiment of the present invention. FIG. 4 illustrates a singlestage, but it is readily understood that the invention may comprisemultiple stages connected to one another,

[0038] In charge pump stage 20, NMOS charge transfer transistor m_(i)has its source connected to node n_(i−1), its gate connected to nodeg_(i), and its drain connected to node n_(i). Pulse train PH injectsenergy into the pump through large capacitor 5 connected to node n_(i).Another pulse train PHA injects energy into the pump through smallcapacitor 11 into node g_(i).

[0039] An auxiliary transistor t_(i) has its drain connected to the gatenode g_(i) to charge transfer transistor m_(i). The source of auxiliarytransistor t_(i) is connected to the source of charge transfertransistor m_(i) (i.e., node n_(i−1)). The gate of auxiliary transistort_(i) is connected to the drain of charge transfer transistor m_(i)(i.e., node n_(i)). The auxiliary transistor t_(i) and the PHA phasepulse train control the gate voltage of the charge transfer transistorm_(i).

[0040] The P-well (PW) of charge transfer transistor m_(i), as well asthe PW of auxiliary transistor t_(i), is preferably isolated from theP-substrate, which may be accomplished with triple-well technology.However, other transistor;architectures may be used to carry out theinvention other than triple-well technology. For example, the P-well maybe isolated from the P-substrate by an SOI structure, such as but notlimited to, an SOS (silicon-on-sapphire) structure formed byheteroepitaxy of silicon on a monocrystalline sapphire substrate by CVD(chemical vapor deposition). Another example is that of SIMOX(separation by ion-implanted oxygen) in which a silicon dioxide layer isformed by ion implantation of oxygen into a silicon monocrystallinesubstrate.

[0041] In accordance with an embodiment or the invention, charge pumpstage 20 may comprise an NMOS transistor N_(i), and inverters I1 and I2.The drain of transistor N_(i) may be connected to Vdd, which generallyis the supply voltage to the particular charge pump stage. The source oftransistor N_(i) may be connected to the positive supply of inverter I2.The gate of transistor N_(i) may be connected to the stage output, whichfor the single stage shown in FIG. 4, may be connected to the source ofthe charge transfer transistor m_(i+1) of the next stage. Pulse trainPHA is connected to the input of inverter 11. which outputs to inverterI2. The output of inverter I2 is connected to the bulk of chargetransfer transistor m_(i). Accordingly, a modified output of pulse trainPHA is input to the bulk of charge transfer transistor m_(i). The bulkof transistor N_(i) may be optionally connected to its source.

[0042] The voltage at the source of transistor N_(i) is designated asVs. Vs is the minimum of Vdd (the positive rail) and the differencebetween the voltage of the stage output (tile drain of the chargetransfer transistor m_(i) of the present stage at node n_(i), whichleads to the source of the charge transfer transistor m_(i+1), of thenext stage) and the threshold voltage (V_(t)) of the charge transfertransistor m_(i) of the present stage. Accordingly, in the precedingnomenclature, Vs=MIN (Vdd, V_(ni−V) _(t)).

[0043] As mentioned hereinabove, during the charge transfer stage thepulse train PHA is high. Alter inversion by inverter I1, the input toinverter I2 is a logic low, which means the output of inverter I2 isdriven to Vs. As mentioned previously, the output of inverter I2 isconnected to the bulk of charge transfer transistor m_(i). Thus, duringthe charge transfer stage, the bulk of charge transfer transistor mi isboosted to Vs, which is the minimum of Vdd and the difference betweenthe voltage of the stage output and the threshold voltage (minimum ofVdd and V_(ni)−V_(t)). This may significantly reduce the bulk effect ofcharge transfer transistor m_(i), and thus increase the efficiency ofstage 20. The bulk voltage at no point can exceed either the source ordrain voltages of any charge transfer transistor m_(i), thusguaranteeing that no latchup or bipolar currents may be activated.Unlike the prior art, the boosting mechanism of the present inventiondoes not depend on any outputs from prior stages, and may be applied tothe all pump stages including the first pump stages. The additionalcomponents in the charge pump stage (transistor N_(i), and inverters I1and I2) may be of minimum size and thus may not occupy significant areaor draw significant additional current. The gate of auxiliary transistort_(i) may be optionally connected to GND or to the PW of charge transfertransistor m_(i) at node v_(i).

[0044] Reference is now made to FIG. 5, which illustrates simulatedwaveforms of the pump stage 20 of FIG. 4. FIG. 5 illustrates voltagelevels at the source side of charge transfer transistor m_(i) (nodesn_(i−1) in FIG. 4) and the drain side of charge transfer transistorm_(i) (node n_(i) in FIG. 4). It is noted that when comparing noden_(i−1) to node n_(i), the average voltage of node n_(i) is greater thanthat of node n_(i−1). However, during the charge transfer phase, whenPHA is high and charge is transferred from node n_(i−1) to node n_(i),the voltage of node n_(i−1) is briefly higher than that of node n_(i)for a short transient period, such transient periods being designated byreference numeral 15 in FIG. 5. During transient period 15, the well ofcharge transfer transistor m_(i) may be boosted as describedhereinabove, which results in a reduced bulk effect, and hence, moreefficient charge transfer (node n¹⁻¹>node n_(i)).

[0045] Accordingly, the voltage level of the bulk of each chargetransfer transistor m_(i) is raised to a level not greater than theminimum of the voltage level of the source and drain of that chargetransfer transistor m_(i). The architecture of the present inventionensures that the P-well/bulk of each charge pump stage is raised to alevel less than or equal to the minimum, during the entire clock cycle,of the source/drain voltage at that stage, which minimizes the bulkeffect, and at the same time ensures that no diodes are forward biased.

[0046] It will be appreciated by person skilled in the art, that thepresent invention is not limited by what has been particularly shown anddescribed herein above. Rather the scope of the present invention isdefined only by the claims which follow:

What is claimed is:
 1. A method for operating a charge pump, the methodcomprising: providing a pulse train which injects energy into a chargepump stage to a gate of a charge transfer transistor of said charge pumpstage; and inputting a modified output from said pulse train to a bulkof said charge transfer transistor such that a bulk voltage of saidcharge transfer transistor is raised to a level not greater than theminimum of a source voltage and a drain voltage of that charge transfertransistor.
 2. The method according to claim 1, wherein the bulk voltageof said charge pump stage is raised to a level below a minimum ofsource/drain voltages of a charge transfer transistor at that stage. 3.The method according to claim 1, wherein said modified output comprisesconnecting said pulse train to an input of a first inverter, whichoutputs to a second inverter, an output of said second inverter beingconnected to the bulk of said charge transfer transistor.
 4. The methodaccording to claim 3, further comprising providing an n-channel metaloxide semiconductor (NMOS) transistor, wherein a source of said NMOStransistor is connected to a positive supply of said second inverter, agate of said NMOS transistor is connected to the drain of said chargetransfer transistor, and a drain of said NMOS transistor is connected toa supply voltage (Vdd) of said charge pump stage.
 5. The methodaccording to claim 4, wherein the source voltage of said NMOS transistor(Vs) is the minimum of Vdd and the difference between the voltage of thestage output and the threshold voltage of said NMOS transistor.
 6. Themethod according to claim 4, wherein the bulk of said NMOS transistor isconnected to its source.
 7. A charge pump stage comprising: a pulsetrain which injects energy into a gate of a charge transfer transistorof said charge pump stage, wherein a modified output of said pulse trainis input to a bulk of said charge transfer transistor such that a bulkvoltage of said charge transfer transistor is raised to a level notgreater than the minimum of a source voltage and a drain voltage of thatcharge transfer transistor during the time said pulse train is active.8. The charge pump stage according to claim 7, wherein said pulse trainis connected to an input of a first inverter, which outputs to a secondinverter, an output of said second inverter being connected to the bulkof said charge transfer transistor.
 9. The charge pump stage accordingto claim 8, further comprising an n-channel metal oxide semiconductor(NMOS) transistor wherein a source of said NMOS transistor is connectedto a positive supply of said second inverter, a gate of said NMOStransistor is connected to the drain of said charge transfer transistor,and a drain of said NMOS transistor is connected to a supply voltage(Vdd) of said charge pump stage.
 10. The charge pump stage according toclaim 9, wherein the source voltage of said NMOS transistor (Vs) is theminimum of Vdd and the difference between the voltage of the stageoutput and the threshold voltage of said NMOS transistor.
 11. The chargepump stage according to claim 8, wherein the bulk of said NMOStransistor is connected to its source.